1. Field of the Invention
The present invention relates, in its more general aspect, to the field of the electronics with nanometric components and to the field of the nano-manufacturing.
In particular, the invention relates to a nanometric architecture or structure with parallel arrays having a multi-spacer structure comprising a plurality of elements or spacers, being substantially bar-like, arranged according to an ordered, lined up configuration.
The invention also relates to a method of making a structure of the above considered type.
2. Description of the Related Art
As it is well known, in the field of the microelectronics the need of realizing circuit configurations of more and more reduced dimensions is particularly felt.
In the last thirty years, the progress of the electronic technology has followed a trend governed by that which is known as “Moore Law”, an empirical law stating that the capacity of storing information in memory devices doubles each eighteen months approximately, whereas the calculation performance of the CPUs (Central Processing Units) improve of a factor each twenty-four months, as reported in the diagram of FIG. 1.
The Moore law is based on the capacity of reducing the geometries of the considered devices and it highlights how dimensions have passed from being equal to 2 μm for the nineteen eighties technologies, to being equal to 130 nm in 2001, to currently being equal to 90 nm.
However, the current technology is quickly reaching the physical limits of its possibilities; in particular, the currently used photolithography processes are subject to drastic dimensional limitations for values being lower than 100 nm.
Forward techniques have thus been developed such as x-ray non optic lithography, extreme ultra-violet lithography and the electronic beam lithography which allow to realize circuit configurations with dimensions in the order of some tens of nanometres.
These techniques, however, require complex instruments characterized by excessively long times of lithographic etching and they thus result too expensive for being applied to a mass industrial manufacturing.
As an alternative, controlled deposition and selective removal techniques of a functional material on a suitable substrate have been developed.
These techniques have allowed for the adjustment of methods for realizing semiconductor substrates suitable for obtaining different typologies of transistors, as for example indicated in the U.S. Pat. Nos. 6,570,220 and 6,063,688 both to Doyle et al.
In particular, in these patents a transistor with field effect is described comprising a sub-micrometric conductive region and, respectively, a relative method for realizing it.
The transistor described in such patent has a channel region comprising a plurality of conductive elements, or spacers, which are lined up and have a length substantially equivalent to that of the channel region, and also comprising a dielectric material to fill in the space between consecutive spacers.
The plurality of lined up conductive elements is realized by means of a method which essentially comprises the steps of realizing, on a silicon substrate by means of lithography, first spacers of a first material whereon, by means of controlled deposition, a layer of a second material is then realized.
The layer of second material is deposited with a thickness approximately corresponding to half of the width of the first spacers.
A selective removal step of the second material follows, carried out by means of anisotropic etching, through which second spacers are formed, each being adjacent to respective side portions of the first spacers, and each having width equal to the thickness of the layer of the second material.
With a subsequent selective chemical etching the first spacers are removed, leaving on the surface of the semiconductor substrate the second spacers. A further step comprising the deposition of a layer of a third material, controlled in the thickness, followed by a selective removal with anisotropic etching, defines third spacers.
These third spacers, each adjacent to respective side portions of the second spacers, have equal width to the thickness of the layer of the third material. By means of a selective chemical etching the second spacers are removed leaving on the surface of the semiconductor substrate solely the third spacers.
The steps of controlled deposition, of anisotropic chemical etching and of selective etching are repeated more times, for realizing spacers of reduced width of 100 Å or less, separated from one another by a distance of about 200 Å.
By finally depositing some dielectric material in the region defined between two consecutive spacers, a conductive region is realized which can be used for realizing a CMOS transistor.
The above method needs, however, a preliminary and accurate programming since each realisation step of an order n (with n≧2) of spacers is followed by a removal step of the spacers of the previous order (n−1), and it is thus initially necessary to provide a suitable distance and a suitable thickness of the first spacers for realizing in the end last spacers of desired dimensions.
In the U.S. Pat. No. 6,664,173 to Doyle et al., a technique is also described for patterning a hardmask gate, for all the typologies of transistors, by using a gate spacer for approaching nanometric masks. This technique provides starting from a unit comprising a substrate whereon first gate and respectively hardmask layers and subsequent second gate and respectively hardmask layers are deposited.
On the second hardmask layer, by means of deposition and further etching steps, a nanometric spacer is defined used as mask for realizing a gate electrode for a first transistor.
From the first hardmask layer of the same unit a structure is realized for a second transistor further to other deposition and etching steps.
Subsequent steps are however required for realizing a MOS device.
Although satisfying the aim, this method is limited in that it allows to realize, although of nanometric dimensions, a single gate electrode for a transistor.
In substance, all the known methods clash with the need of realizing nanometric structures and provided with suitable conduction and control terminals for using them as semiconductor electronic devices.